A three-dimensional integrated circuit (3D IC ) is a chip in which two or more layers of active electronic components are integrated both vertically and horizontally into a single circuit. The semiconductor industry is being hotly pursuing this emerging technology in many different forms, as result the full definition is still somewhat fluid.
Flip chip, memory on logic
The first approach to talk about is flipping one chip and attaching it to the top of another. This is done by creating bonding area on each chip, growing (usually copper) microbumps to create die-die interconnect at a pitch of approximately 50um. The big user of this technology is in the digital camera chips. The CCD image sensor is a actually thinned to the point that it is transparent to light and then attached to the image processing chip. The light from camera lens passes through the silicon to the CCD unobstructed by interconnect etc which is all on the other side of the sensor.
Through Silicon Vias (TSVs)
The key technology for real 3D chips is the through-silicon-via (TSV). This is a via that goes from the front side of the wafer (typically connecting to one of the lower metal layers) through the wafer and out the back. TSVs vary in the diameter from 1 to 10um, with depth from 5 to 10 times the width. A hole is formed into wafer, lined with an insulator and filled with copper or tungsten. Finally the water is thinned to expose the backside of the TSVs. Note that this mean that the water itself ends up merely 10-100um thick. Silicon is being brittle, so one of the challenges is handling wafers this thin both in the fab and when they have to be shipped to an assembly house. The water must be bonded to some more robust substrate (glass or silicon) before thinning and, in some cases, may be separated during assembly. The wafer is thinned using CMP (chemical mechanical polishing, similar to how the planarization is done between metal layers in a normal semiconductor process) until the TSVs are almost exposed. More silicon is etched away to reveal the TSVs themselves.
There are two classes of true 3D chips which are being developed today. The first is known as 2½D where a so called silicon interposer is created. The interposer do not contain any active transistors, only interconnect (and perhaps decoupling capacitors), thus avoiding the issues of threshold shift mentioned above. The chips are attached to interposer by flipping them so that the active chips do not require any TSVs to be created. True 3D chips have TSV going through active chips and, in the future, have potential to be stacked several die high (first for low-power memories where the heat and power distribution issues are less critical). The active die themselves do not have any TSV, only the interposer. This means that active die can be manufactured without worrying about TSV exclusion zones or threshold shifts. They needed to be microbumped ofcourse, since they are not going to be conventionally wire-bonded out. The picture above shows (not to the scale, of course) the architecture.